library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity memory_block is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0); --адрес
           WE : in  STD_LOGIC; --резрешение записи
           RD : in  STD_LOGIC; --разрешение чтения
           D : in  STD_LOGIC_VECTOR(7 downto 0); --вход
           Q : out  STD_LOGIC_VECTOR(7 downto 0)); --выход
end memory_block;

architecture BEH of memory_block is
    type mem_type is array (0 to 255) of std_logic_vector(7 downto 0);
    signal mem : mem_type;

begin
    process(A, WE, RD)
    begin
        if RD = '1' then
            Q <= mem(to_integer(unsigned(A)));
        end if;

        if WE = '1' then
            mem(to_integer(unsigned(A))) <= D;
        end if;
    end process;
end BEH;